Registers of Processor IA32
Processors IA32 (32-bit Intel Architecture) have a set of high-speed memory cells located
in the immediate vicinity of the processor core, which are called registers. These are 4 32-bit
registers of general destination:
In addition, control registers CR0 ... CR4, memory control registers GDTR, IDTR, LDTR, TR, debug registers DR0 ... DR7, test registers TR1 ... TR12 are also present in IA32 processor.
In all modern IA32 architecture processors, there are registers of SIMD-extension (Single Instruction - Multiple Data): 64-bit registers of MMX-extensions MMX0 ... MMX7, 128-bit registers of SSE-extensions XMM0 ... XMM7.
The fractional line which is present in designation of a part of the registers indicates the permissible variants of addressing to these registers, this is related to the task of ensuring the compatibility of 32-bit processor with commands of processors of previous generations (16-bit and 8-bit). For example, the program can address either the 32-bit register EAX, or its lower word AX (emulation of 16-bit processor), or each byte of the lower word AH or AL (emulation of 8-bit processor). The codes of operations with AX, AH and AL in 32-bit processor remained the same as those in the 16-bit or 8-bit processor.
General purpose registers can be used to perform arithmetic operations (the operands are allocated in them), to store addresses or pointers. At the same time, general purpose registers have a specific specialization. So, in the register EAX the processor records the result of arithmetical or logical operation; the register EBX is used to store the start address of some sequence of data in the memory; the register ECX is used as a counter of repeats in cycles; and in the register EDX the processor writes the highest part of result of the operation, if this part does not fit in the register EAX.
The registers ESI and EDI are designed for operations over data arrays (chain operations). The register ESI contains the address of the next element of array to be processed. The result of processing is placed at the address contained in the register EDI.
The registers EBP, ESP, EIP contain, respectively, a pointer to the base of frame of the stack, a pointer to the top of the stack, a pointer to the next command to be executed by the processor.
Segment registers contain addresses of code segment, data segment, stack segment (CS, DS, SS). In the program it can be organized 3 additional data segments, to set their addresses, the registers ES, FS, GS
Bits (flags) of the register EFLAGS, depending on their value (1 - flag is up, 0 - flag is down), carry information about the state of processor after the execution of the operation and about its result.
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